In order to screen defective products occurring at the initial stage of manufacturing of semiconductor devices or wafers, accelerated tests have hitherto been performed by causing semiconductor devices and wafers to work under high-temperature, high-voltage conditions. These tests are called burn-in. In recent years, a technique for performing burn-in at the wafer level (hereinafter referred to as wafer-level burn-in) has been frequently carried out. In wafer-level burn-in, the inspection is performed by inputting a high voltage and signals to the power-supply electrode of the device and a plurality of input/output electrodes, respectively.
Usually, in the case of a semiconductor wafer, the possibility that a plurality of devices fabricated on the wafer are all conforming products is low, and both defective products and conforming products are mixed on the wafer. In wafer-level burn-in, the inspection is often carried out by applying stress to only conforming products and insulating nonconforming products so that they do not work.
The construction of a probe card (a semiconductor inspection apparatus) in conventional wafer-level burn-in will be described here with reference to FIGS. 7A and 7B.
FIG. 7A is a plan view that shows the rear surface of a conventional probe card, and shows the appearance of a surface of the probe card opposite to the surface that comes into contact with each semiconductor IC 11. FIG. 7B is a sectional view that shows the cross-sectional structure of the conventional probe card.
As shown in FIG. 7B, a plurality of semiconductor ICs 11 are formed on a semiconductor wafer 10, and an inspection electrode 12 is formed on each of the semiconductor ICs 11. Although usually a plurality of inspection electrodes 12 are formed on each of the semiconductor ICs 11, for the sake of simplicity of illustration, FIG. 7B shows a case where one inspection electrode 12 is formed on each of the semiconductor IC 11. The alternate long and short dash lines in FIG. 7A indicate the positional relationship of the semiconductor ICs 11 when a probe card is placed on the semiconductor wafer 10 during the inspection.
As shown in FIGS. 7A and 7B, a probe terminal 21 corresponding to each of the inspection electrodes 12 of the semiconductor IC 11 is formed on a surface of a card body 20 constituting the probe card, and a PTC (positive temperature coefficient) element 22, which is a current breaking circuit performing breaking operation according to the amount of current, is formed in an area corresponding to the probe terminal 21 on the rear surface of the card body 20. And in an area of the card body 20 where the probe terminal 21 is formed, a contact 23 that pierces through the card body 20 in the front and rear direction is formed. The front surface side of the contact card 23 is connected to the probe terminal 21, and the rear surface side of the contact 23 is connected to the PTC element 22.
An external electrode 24 to which a voltage is applied from an external device is formed in a peripheral edge portion of the rear surface of the card body 20, and on the rear surface of the card body 20, a common voltage supply line 25 that connects the external electrode 24 and each of the PTC elements 22 extends in a branching manner. As a result of this, when a voltage is applied to the external electrode 24, the applied voltage is applied to each of the probe elements 21 via the common voltage supply line 25, the PTC elements 22 and the contacts 23. Incidentally, the common voltage supply line 25 may be constructed in such a manner that the common voltage supply line 25 is connected, in a shared manner, to the PTC elements 22 corresponding to the semiconductor ICs 11 for each row and column on the semiconductor wafer 10 by a plurality of common voltage supply lines 25 branching off from the external electrode 24. The common voltage supply line 25 may also be a power-supply voltage supply line for applying a power-supply voltage or a grounding-voltage supply line for applying a grounding voltage.
A polymer-based PTC element, a ceramic-based PTC element formed from barium titanate (BaTiO3) and the like are used as the PTC element 22.
Incidentally, the polymer-based PTC element is a resistance element in which conductive carbon and an insulating polymer, such as polyolefin and fluororesin, are mixed, and in a normal state the carbon dispersed in the polymer forms a large number of conducting paths. Therefore, the polymer-based PTC element has a low specific resistance value. However, when the temperature of the polymer-based PTC element is gradually raised from the normal state, the conducting paths of the carbon are gradually cut and the polymer-based PTC element exhibits gentle PTC characteristics, because the coefficient of thermal expansion of the polymer is higher than the coefficient of thermal expansion of the carbon. And when a prescribed temperature is exceeded, the PTC effect appears abruptly. That is, because volume changes resulting from the melting of the polymer, which are as high as several tens percent, cut the conducting paths of the carbon one by one, the resistance value increases by several orders of magnitude, for example, on the order of five orders of magnitude.
In the case of the ceramic-based PTC element, it is possible to select a prescribed temperature at which the PTC effect exhibits itself by adjusting the amount of an impurity added. For example, in a case of a ceramic-based PTC element formed from barium titanate, by adding Pb as an impurity, it is possible to cause the temperature at which the PTC effect exhibits itself to shift to the high-temperature side. The temperature at which the PTC effect exhibits itself shifts to the high-temperature side with increasing amount of Pb added.
The phenomenon in which the resistance value of the PTC element becomes very high compared to that in a steady state due to the flow of a large amount of current in the PTC element or due to a temperature rise of the PTC element is called a trip. In a steady state the resistance value of the PTC element is stable at a very low value with respect to a load. However, when the amount of a flowing current exceeds a standard (a trip current) determined by the characteristics of the PTC element, the resistance of the PTC element increases due to self-heating and the current that flows through the PTC element is limited to a very small amount. Once the PTC element comes to a trip state, the PTC element becomes stable in the condition in which the resistance value has increased and, therefore, the PTC element continues to maintain the trip state. And the PTC element returns automatically to the steady state when the power source is shut off and the PTC element temperature returns to the initial condition or when the voltage of a circuit becomes sufficiently low (when the calorific value of the PTC element becomes small compared to its heat release).
As described above, because a probe card used for wafer-level burn-in is provided with a voltage supply line that supplies a voltage to each semiconductor IC and PTC elements added on the power supply line so as to correspond to each of the semiconductor ICs, a large amount of current flows through DC-defective semiconductor ICs during wafer-level burn-in. Therefore, the resistance of the PTC element increases and it is possible to insulate the semiconductor ICs.